Designing the Next Version of TPUs with Reinforcement Learning and Graph CNNs

(T) A team of Google researchers developed a reinforcement learning system to design the billions of transistors in the next version of Google’s Tensor Processing Unit (TPU) chips optimized for computing TensorFlow applications. The system uses a graph convolutional neural network architecture capable of learning rich and transferable representations of the TPU from a dataset of 10,000 chip designs. It generates the design in six hours rather than the usual span of weeks spend by hardware engineers, with comparable or better metrics for power consumption, performance, and chip area.

Abstract of the paper:

Chip floorplanning is the engineering task of designing the physical layout of a computer chip. Despite five decades of research, chip floorplanning has defied automation, requiring months of intense effort by physical design engineers to produce manufacturable layouts. Here we present a deep reinforcement learning approach to chip floorplanning. In under six hours, our method automatically generates chip floorplans that are superior or comparable to those produced by humans in all key metrics, including power consumption, performance and chip area. To achieve this, we pose chip floorplanning as a reinforcement learning problem, and develop an edge-based graph convolutional neural network architecture capable of learning rich and transferable representations of the chip. As a result, our method utilizes past experience to become better and faster at solving new instances of the problem, allowing chip design to be performed by artificial agents with more experience than any human designer. Our method was used to design the next generation of Google’s artificial intelligence (AI) accelerators, and has the potential to save thousands of hours of human effort for each new generation. Finally, we believe that more powerful AI-designed hardware will fuel advances in AI, creating a symbiotic relationship between the two fields.

Following is the published paper in Nature A graph placement methodology for fast chip design“, and an earlier paper in arXiv “Chip Placement with Deep Reinforcement Learning“.

Note: The picture above is Google’s TPU data centers.

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